1. Field of the Invention
The present invention relates to the field of computer system or processor architectures. Specifically, the present invention pertains to the use of general purpose registers in a processor architecture.
2. Prior Art
Most modem computers provide a register set for the manipulation of data by a central processing unit (CPU). For example, the 80386 microprocessor manufactured by Intel Corporation of Santa Clara, Calif. provides eight general purpose registers and various processing instructions for manipulating data in those registers. The use of these registers and the associated processing instructions provides a high speed means for manipulating data. The number of clock cycles required to access information stored in a general purpose register is much less than the number of cycles required to access information in a memory, such as a dynamic random access memory (DRAM).
Currently, many programs require more registers than are provided by current computer architectures. In many cases, the code generated by high level programming languages (i.e., C, FORTRAN, or ADA) requires the use of more registers than the architecture provides. If enough general purpose registers are not available, data must be spilled to main memory. Access to main memory, however, is significantly slower than moving data between general purpose registers. Requiring a CPU to write information to main memory and then later read values back from memory significantly slows the operation of the computer.
It is advantageous to have a greater number of general purpose registers for a particular computer architecture. However, software operating on the computer system must be significantly modified to take advantage of the additional registers. Additionally, by increasing the number of general purpose registers provided in a computer architecture, the task of managing register allocation becomes more difficult.
In conventional computers, the identification of registers is encoded into a field of bits within register manipulation instructions. These register encodings identify the register or registers that are manipulated by the instruction. Typically, however, a limited number of bits is provided for each instruction. Thus, a limited number of bits is provided for encoding register identities in instructions. In conventional computer systems, therefore, the number of registers provided by the computer system architecture is limited by the size of the instruction format.
Thus, an improved computer system architecture providing an expanded register set is needed.